Semiconductor transistors, in particular field-effect controlled switching devices such as a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) or an Insulated Gate Bipolar Transistor (IGBT), have been used for various applications including but not limited to use as switches in power supplies and power converters, electric cars, air-conditioners, and even stereo systems. Particularly with regard to power devices capable of switching large currents and/or operating at higher voltages, low on-state resistance Ron, high breakdown voltages Ubd, high robustness and/or good softness are often desired.
To achieve low on-state resistance Ron and high breakdown voltages Ubd, compensation semiconductor devices were developed. The compensation principle is based on a mutual compensation of charges in n- and p-doped regions, which are often also referred to as n- and p-doped pillar regions, in the drift zone of a vertical MOSFET.
Typically, the charge compensation structure formed by p-type and n-type regions is arranged below the actual MOSFET-structure, with its source, body regions and gate regions, and also below the associated MOS-channels that are arranged next to one another in the semiconductor volume of the semiconductor device or interleaved with one another in such a way that, in the off-state, their charges can be mutually depleted and that, in the activated state or on-state, there results an uninterrupted, low-impedance conduction path from a source electrode near the surface to a drain electrode arranged on the back side.
By virtue of the compensation of the p-type and n-type dopings, the doping of the current-carrying region can be significantly increased in the case of compensation components, which results in a significant reduction of the on-state resistance Ron despite the loss of a current-carrying area. The reduction of the on-state resistance Ron of such semiconductor power devices is associated with a reduction of the heat generated by the current in the on-state, so that such semiconductor power devices with charge compensation structure remain “cool” compared with conventional semiconductor power devices.
Meanwhile, switching losses ESL of power semiconductor devices have become more important. For power compensation devices, both “normal” losses EOSS which are due to the output charge QOSS stored in the space charge region formed in the off-state and during reverse bias, respectively, and so-called passive losses (sometimes also referred to as parasitic losses) Epas which are due to floating semiconductor regions (floating p-doped pillar regions) in a peripheral area may contribute to the switching losses (ESL=EOSS+Epas). To ensure high breakdown voltages Ubd, floating p-doped pillar regions are often used in the peripheral area surrounding the active area with active MOSFET-cells of vertical power compensation devices. If the floating p-doped pillar regions are depleted during the off-state, the holes have to flow through low-doped (high resistive) n-type semiconductor regions. This may result in comparatively high passive losses Epas.
Accordingly, there is a need to improve semiconductor devices with charge compensation structures and manufacturing of those semiconductor devices.